Ethernet Controller IP RTL / Logic Design Engineer

Location: Burlington, VT (or remote-support/work from home considered on a case-by-case basis)

Company Profile:
Encore Semi is a rapidly growing and successful Engineering Services company headquartered in San Diego, California. Encore Semi has a large portfolio of tier1 customers and engineers across the United States and Canada. Our Subject Matter Experts and teams of experts contribute to customer projects in the areas of SoC design and embedded software life-cycle. Our focus and promise is to provide high-value to customers through acceleration, performance improvement, optimization, and risk mitigation.

Department Profile:
In support of the high-demand from our customers, the Front-End Design Group is expanding and recruiting new members. This engineering service group is looking for RTL /Logic developers to implement microarchitecture specifications in RTL efficiently with high quality.

As SOC designs are becoming optimized more and more, there is a critical need for RTL / Logic Designers to develop reusable IP blocks providing advanced and specialized features for these SOC designs. The Encore Semi Front-End Logic team is looking for experts in RTL development and Logic Designs to create the RTL models delivering these advanced features. These experts would be targeting advanced implementations of Ethernet controllers (based on the IEEE 802.3 standards).

Essential Duties/Responsibilities/Functions/Tasks:
Based on experience and knowledge of Ethernet protocols, especially the IEEE 802.3 standard, will work with microarchitects and written specifications to create RTL code and a Logic Design delivering a reusable IP design for customers. The main deliverable will be a configurable “soft” IP – Verilog RTL code able to be plugged into multiple SOC designs. As part of the design process, the designer will need to enable the RTL to run through Cadence synthesis tools to ensure it is synthesizable by the end SOC customer. In addition, they will work closely with verification engineers to deliver a high quality, bug free design.

Minimum Qualifications:

• RTL / Logic Design experience using Verilog to create an RTL IP module for a networking or Ethernet controller.
• Knowledge of the IEEE 802.3 Ethernet protocols, especially link training and auto-negotiation.
• Experience with synthesis of RTL into a netlist and incorporating feedback from synthesis runs back into the RTL design.
• BSEE or equivalent; 10+ years of RTL / Logic Design experience.

Preferred Qualifications:

• Knowledge or experience with high-speed networking designs including 100G Ethernet.
• Experience with Cadence NCSim RTL Development / Simulation and Synopsys Design Compiler synthesis environments.
• Experience creating stand-alone IP modules for delivery to SOC customers in other organizations or, even, companies.
• Creation or modification of RTL specifications based on Standards (such as IEEE) or customer supplied requests.

Encore Semi Culture & Full-time Benefits:

Culture & Benefits